1. Field of the Invention
The present invention relates to a differential amplifier circuit or differential input circuit formed in a semiconductor substrate, and more particularly, to a differential amplifier circuit or differential input circuit which suppresses the effects of variations in transistor characteristics caused by variations in manufacture processing and is not influenced by level fluctuations in the differential input signal.
Moreover, the present invention relates to a pull up-type differential bus driver and a differential bus driving method suitable for use in cases where differential signals are transmitted between semiconductor chips.
2. Description of the Related Art
Differential amplifier circuits or differential input circuits (hereinafter, simply called differential amplifier circuits) comprising a pair of MOS transistors, differential inputs being supplied respectively to the gates thereof and an output being generated at the drains thereof, are widely used. In a differential amplifier circuit of this kind, a current source is connected to the source electrodes of a pair of MOS transistors and supplies a fixed current thereto, differential inputs supplied to the gates are compared and the conductivity of one of the pair of MOS transistors is raised whilst the conductivity of the other transistor is lowered.
In cases where signals of small amplitude, such as 100 mv, for example, or differential input signals having a large fluctuation in the central voltage of the amplitude are supplied as differential inputs, generally, the operation of the differential amplifier circuit is stabilized by holding the current from the aforementioned current source at a uniform value as far as possible.
FIG. 1 is a diagram showing an example of a conventional differential amplifier circuit. This differential amplifier circuit comprises: a pair of N-channel input MOS transistors N1, N2, wherein differential inputs IN, /IN are supplied respectively to the gates thereof and the sources thereof are connected mutually; load circuits L1, L2 provided between the drains thereof and a first power source Vdd; and a current source I1 provided between the sources and the second power source Vss. An amplified output is generated at the drain terminal nl of transistor N2 in accordance with the differential inputs IN, /IN. This output nl is supplied to the input of a CMOS inverter consisting of a P-channel MOS transistor P3 and N-channel MOS transistor N3.
FIG. 2 is a diagram showing a further example of a conventional differential amplifier circuit. This differential amplifier circuit also comprises a pair of input MOS transistors N1, N2, load circuits L1, L2, and a current source I1. Moreover, in the differential amplifier circuit in FIG. 2, the drain terminal n1 of the transistor N2 is connected to the gate of a P-channel output MOS transistor P4, and the junction point n3 between the output MOS transistor P4 and a current source I2 is supplied to the input of a CMOS inverter. This circuit differs from the differential amplifier circuit in FIG. 1 in that the signal n3, which is an inverse amplification of the signal from drain terminal n1, is supplied to a CMOS inverter.
In the aforementioned conventional differential amplifier circuit, if the voltage of input IN is lower than the inverse input /IN, then transistor N2 switches on and the voltage of node n1 assumes level L, whereas if, conversely, the voltage of input IN is higher than the inverse input /IN, then transistor N2 switches off and the voltage of node n1 assumes level H. In the differential amplifier circuit in FIG. 1, level L or level H is generated at output n2 of the inverter, in accordance with level H or level L at node n1. In the differential amplifier circuit in FIG. 2, level L or level H is generated at node n3 and level H or level L is generated at the output n2 of the inverter, respectively, in accordance with level H or level L at node n1.
FIG. 3 is a diagram illustrating problems associated with the prior art examples described above. FIG. 3A shows the relationship between the outputs n1, n3 of the aforementioned differential amplifier circuit and the threshold value VthC of the CMOS inverter, and FIG. 3B shows the voltage level of the output n2 of the CMOS inverter corresponding to same.
The outputs n1, n3 of the differential amplifier circuit assume level H and level L having prescribed amplitudes, without performing a full swing between the power sources Vdd and Vss. In contrast to this, the output n2 of the CMOS inverter does make a full swing, assuming either level H, which is the level of the higher power source Vdd, or level L, which is the level of the lower power source (ground) Vss. On the other hand, if the differential amplifier circuit is formed as part of an integrated circuit on a semiconductor substrate, then variations will arise in the characteristics of the MOS transistors due to variations in processing. For example, if a variation in characteristics arises whereby the drive capacity of N-channel MOS transistors is raised, then the impedance of the MOS transistor N2 when conducting will fall, and hence the central voltage of the amplitude at node n1 will tend to fall. In other words, it will deviate from the solid line in FIG. 3 and follow the dotted line. If, conversely, a variation in characteristics arises whereby the drive capacitor of the N-channel MOS transistor is reduced, then the impedance of the MOS transistor N2 when conducting will rise, and hence the central voltage of the amplitude at node n1 will tend to rise. In other words, it will deviate from the solid line in FIG. 3 and follow the broken line.
Upward or downward fluctuation in the central value of the amplitude of output n1 caused by variations in processing is particularly notable in cases where P-channel MOS transistors are used in the load circuits L1, L2 and the drive capacity of the P-channel MOS transistors varies in the opposite direction to the variation in the drive capacity of the N-channel MOS transistors. Even in cases where P-channel output MOS transistors are provided as illustrated in FIG. 2, the central value of the amplitude at output n3 will similarly vary either in an upward or downward direction due to variations in processing.
If the outputs n1 or n3 from the differential amplifier circuit vary as illustrated in FIG. 3, then either one of the P-channel transistor P3 or N-channel transistor N3 in the subsequent CMOS inverter driven by these outputs n1, n3, will not be able completely to assume a non-conducting state, thereby resulting in a through current from power source Vdd to Vss in the CMOS inverter. The generation of through current in this way, in addition to increasing power consumption, also leads to problems in that the output n2 of the CMOS inverter cannot be amplified completely to the power source level.
Moreover, to describe a second problem, when the outputs n1, n3 of the differential amplifier circuit are higher than the threshold voltage VthC of the CMOS inverter, as illustrated in FIG. 3, the output thereof assumes level L, whereas when outputs n1, n3 are lower than VthC, then the output assumes level H. However, if the voltage of the outputs n1, n3 of the differential amplifier circuit vary upwards or downwards as shown in FIG. 3 due to processing in manufacture, then the timing of level H or level L of the input with respect to the threshold voltage of the CMOS inverter will differ. As a result, the input rise propagation delay time and the input fall propagation delay time in the CMOS inverter will run contrary to each other, leading to significant variations in characteristics during high-speed operation. Since the threshold voltage VthC of the CMOS inverter is a value determined by the ratio of current values in the P-channel transistor P3 and the N-channel transistor N3, this threshold voltage VthC also varies with fluctuations in transistor characteristics. However, the magnitude of this variation in threshold voltage is small compared to the variations in the output level of the differential amplifier circuit.
A third problem is that when there is a variation in the central voltage of the amplitude of the differential inputs to the differential amplifier circuit, this impedes the differential operation of the input transistors of the differential amplifier circuit. For example, in some cases, a differential input from an external circuit having a different power system may become extremely low if the power system of the semiconductor device in which the differential amplifier circuit is provided is taken as a reference. For instance, if the differential input has an amplitude of the order of 100 mV whilst the central value of the amplitude of the external differential input takes a low value of approximately 1 V, for example, then the gate-source voltage in the N-channel input transistors N1, N2 of the differential amplifier circuit will become lower than the threshold voltage of the transistors and both transistors N1 and N2 will assume a non-conducting state. Consequently, it will become impossible to conduct a voltage comparison operation with respect to the differential inputs. Input transistors N1, N2 are generally of an enhancement-type composition, and therefore differential input signals supplied to the gates thereof need to having a central value level which is a certain degree higher than the ground voltage Vss.
FIG. 16 is a circuit diagram showing the principal part of one example of a signal transmission system containing one example of a conventional pull up-type differential bus driver. In FIG. 16, 1 is a semiconductor device forming a driver, 2 is a semiconductor device forming a receiver, 3 and 4 are signal lines providing a connection between semiconductors 1 and 2, 5 and 6 are terminal resistances, 7 is a terminal voltage line supplying terminal voltage VT1, and 8 is a terminal voltage line supplying terminal voltage VT2.
In the semiconductor device 1, 9 is a conventional pull up-type differential bus driver, SIN and /SIN are differential input signals input from the internal circuitry (not illustrated) to the pull up-type differential bus driver 9, and 10 and 11 are signal output terminals whereby the differential output signals SOUT, /SOUT are output from the pull up-type differential bus driver 9.
Furthermore, in the pull up-type differential bus driver 9, 12 is a power source line supplying power voltage V1, 13 is a constant current source, 14 denotes switching means which switches on and off in accordance with the input signal SIN, and 15 denotes switching means which switches on and off in accordance with the input signal /SIN.
In a signal transmission system constituted in this way, when the input signal SIN is at level H and input signal /SIN is at level L, then switching means 14 turns on and switching means 15 turns off, and hence the signal line 3 is pulled up by the current output from the constant current source 13 and a level H signal is transmitted in the signal line 3, whilst the signal line 4 is pulled down via terminal resistance 6 and a level L signal is transmitted in the signal line 4.
If, on the other hand, the input signal SIN is at level L and input signal ISIN is at level H, then switching means 14 turns off and switching means 15 turns on, and hence the signal line 3 is pulled down via terminal resistance 6 and a level L signal is transmitted in signal line 3, whilst signal line 4 is pulled up by the current output from fixed current source 13 and a level H signal is transmitted in signal line 4.
In the signal transmission system illustrated in FIG. 16, no problems occur when the terminal voltages VT1, VT2 are lower then the power voltage V1, but it is conceivable that, for a reason of any kind, terminal voltage VT1 or terminal voltage VT2 may increase and become higher than power voltage V1, or that the power voltage V1 may fall such that terminal voltage VT1 or terminal voltage VT2 becomes higher than power voltage
In such cases where the terminal voltage VT1 or terminal voltage VT2 has become higher than the power voltage V1 and the voltage in signal line 3 or the voltage in signal line 4 has become higher than the power voltage V1, there is a risk that, in the semiconductor device 1, a current will flow into the power line 12 via switching means 14 or switching means 15, and the constant current source 13, thereby leading to malfunction.
Therefore, it is an object of the present invention to provide a differential amplifier circuit or differential input circuit whereby fluctuations in output level are suppressed even when there are variations in transistor characteristics due to the manufacturing process, or the like.
It is a further object of the present invention to provide a differential amplifier circuit or differential input circuit whereby a differential amplification operation can be carried out correctly, even in cases where the central values of the amplitude of the differential input signals differ widely.
It is also an object of the present invention to provide a pull up-type differential driver which is devised such that there is no influx of current from the signal line side to the power source side, even if, for any reason, the voltage in the signal lines has become higher than the power voltage, thereby providing increased reliability and avoiding malfunctions due to influx of current from the signal line side to the power source side in cases where a pull up-type differential bus driver is installed in a designated semiconductor device.
Moreover, it is a further object of the present invention to provide a differential driving method which is devised such that there is no influx of current from the signal line side to the power source side even when, for any reason, the voltage in the signal lines has become higher than the power voltage, thereby providing increased reliability and avoiding malfunctions due to influx of current from the signal line side to the power source side in cases where a pull up-type differential bus driver is installed in a designated semiconductor device.